Estimation of the noise immunity of immitance logic elements

Abstract

The noise immunity of immitance logic elements (ILEs) realized on the basis of a transistor generalized immitance converter (GIC) is analytically estimated. It is shown that this estimate is determined by the effect of static interferences (temperature and supply voltage changes), high-frequency interferences (reference oscillation power and frequency changes), and immitance interferences (changes of the real and imaginary components of the immitance to be converted and changes of internal interferences related with the GIC potential instability). It is suggested to use the relative noise immunity coefficients for the immitance levels of logic 0-γ C , and logic 1-γ L , for analytical estimation of the ILE noise immunity. The admissible range of variation of these immitance levels are 0 < γ C < 1 and 0 < γ L < 1. The noise immunity is quantitatively estimated. As a result, it is found that, within the reference frequency 0.4–1.5 GHz, an ILE’s reserve of the noise immunity to the instability of the imaginary component of the high-Q input immitance exceeds 80% and that the noise immunity reserve is reduced by no more than 5% when the supply voltage changes by 30% and when the temperature changes by 40%.