Abstract
For the fabrication of very high voltage SiC devices, it is essential to know the surface recombination velocity to accurately control the carrier lifetime. This study shows experimental results on the carrier lifetime in free-standing n-type 4H-SiC epilayers with several thicknesses and under two surface conditions to estimate the surface recombination velocity. The surface with chemical–mechanical polishing (CMP) was found to have lower surface recombination velocities than the as-grown epilayer surface. Similarly, the surface recombination velocity after CMP was low on the Si-face compared with that on the C-face. In addition, the surface recombination velocities on Si- and C-faces after CMP were quantitatively evaluated by comparison of experimental results with numerical calculations.
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