Estimation of partition size for I/sub DDQ/ testing using built-in current sensing

Abstract

I/sub DDQ/ testing of CMOS circuits can detect faults that are not easily detected using traditional test techniques. The quiescent current drawn by CMOS devices is very small, and certain faults in a device may cause this current to increase by several orders of magnitude. Current sensors are used to detect abnormalities in the quiescent current. The quiescent current in a circuit can be monitored using an external current sensor or a Built-in Current Sensor (BICS). BICS show improvement in speed and resolution over external current sensors. When connecting a BICS to a circuit, the site of the partition, propagation delay and settling time of the circuit must be taken into consideration. Variations in process parameters may cause variations in the fault-free and faulty I/sub DDQ/ in a CMOS device. As the number of gates in a device increase, the distributions of fault-free and faulty I/sub DDQ/ may start to overlap, thus making it impassible to distinguish between fault-free and faulty currents in a device. Adding a BICS to a circuit may increase the settling time of the circuit, due to the lumped capacitance across the BICS. Monte Carlo simulations have been performed on circuits of various sizes and levels to estimate the partition size for I/sub DDQ/ testing using BICS.