Estimation of Muon-Induced SEU Rates for 65-nm Bulk and UTBB-SOI SRAMs

Abstract

Negative and positive muon-induced single-event upset (SEU) rates were estimated for 65-nm bulk and ultrathin body and thin buried oxide silicon-on-insulator (UTBB-SOI) static random access memories (SRAMs). The SEU cross sections for muon incidence on the two SRAMs were experimentally characterized and compared. The experimental results showed that the negative muon SEU cross sections for the bulk SRAM are significantly larger than those for the UTBB-SOI. Estimation of muon SEU rates at ground level was performed using the experimental results and the Monte Carlo simulation with the Particle and Heavy Ion Transport code System (PHITS). The estimated muon SEU rates were compared with the measured neutron SEU rates. The contribution of muons was found to be considerably smaller than that of neutrons. Attenuation effect of muons and neutrons in a five-story building was also investigated by particle transport simulation with PHITS. The muon SEU rate on the first floor was estimated to be at most 10% of the neutron SEU rate on the same floor.