Abstract
This work deals with the analysis of spectrum generation from advanced integrated circuits in order to better understand how to suppress the generation of high harmonics, especially in a given frequency band, to design and implement noise-free systems. At higher frequencies, the spectral components of signals with sharp edges contain more energy. However, current closed-form expressions have become increasingly unwieldy to compute higher-order harmonics. The study of spectrum generation provides an insight into suppressing higher-order harmonics (10th order and above), especially in a given frequency band. In this work, we discussed the influence of transistor model quality and input signal on estimates of the harmonic contents of switching waveforms. Accurate estimates of harmonic contents are essential in the design of highly integrated micro- and nanoelectromechanical systems. This paper provides a comparative analysis of various flip-flop/latch topologies on different process technologies, i.e., 130 and 65 nm. An FFT plot of the simulated results signifies that the steeper the spectrum roll-off, the lesser the content of higher-order harmonics. Furthermore, the results of the comparison illustrate the improvement in the rise time, fall time, clock-Q delay and spectrum roll-off on the better selection of slow-changing input signals and more accurate transistor models.
Highlights
Integrated circuit designs are becoming more complex day by day, and the integration of ten billion transistors on the same die with clock frequencies above several gigahertz makes it difficult to implement cost-effective and reliable systems
Transistor model quality and choice of input signal play a significant role in the exact estimation of switching harmonics
All simulations presented in this paper are performed on BSIM 3 and BSIM 4 transistor models using Cadence Spectre
Summary
Integrated circuit designs are becoming more complex day by day, and the integration of ten billion transistors on the same die with clock frequencies above several gigahertz makes it difficult to implement cost-effective and reliable systems. The development of reliable and cost-effective mixed-signal and RF systems depends on system-on-chip (SOC). We need accurate and reliable design tools for the estimation of switching noise coupled from the digital part into analog to implement noise-free integrated circuits for use in future-generation electromechanical systems. Transistor model quality and choice of input signal play a significant role in the exact estimation of switching harmonics. All simulations presented in this paper are performed on BSIM 3 and BSIM 4 transistor models using Cadence Spectre
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