Esterel methodology for complex system design

Abstract

The design of smart devices and complex Systems-On-a-Chip calls for new system level methods and tools to cope with short time-to-market constraints, technical complexity and system validation growing burden. The methodology proposed here is to use Esterel synchronous models on top of C/C++ or HDL languages to handle reactive and control system aspects. The first advantage is to obtain better intelligibility and modularity of designs. The second benefit is reduced system testing time and better confidence by introducing formal verification at early stages of designs. In this paper, we present the Esterel methodology and design. We illustrate its benefits by presenting the design of a Direct Memory Access module which was extracted from work on a DSP based mobile communication SOC architecture.