Abstract
Apart from ESD tests at system level, e.g. according to IEC 61000-4-2, the investigation of the EMC immunity of individual ICs is becoming increasingly important: an ESD sensitive IC could cause problems in subsequent system level tests when in use. Knowing in advance what to expect from an IC can help save time and money in the design process. An appropriate component level test bench is therefore required. Using standard ESD generators (system level test methods) for component level tests can lead to unexpected results. This paper describes problems that can arise when using standard ESD generators in a customised test set-up whereby a microcontroller is used as a DUT (the tested IC) for demonstration purposes.
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