ESD Stress Effect on Failure Mechanisms in GaN-on-Si Power Device

Abstract

This paper reports investigation of failure mechanisms of GaN-on-Si power device under electrostatic discharge (ESD) stress using on-wafer transmission-line pulse (TLP) testing. Hot-hole injections under the gate and filament formation in the buffer layer are examined by monitoring the threshold voltage (Vth) and on-resistance (Ron) subjected to a floating gate or an off-state gate voltage. Distinct and continued degradation has been observed after the ESD stress is removed indicating a slow de-trapping process due to deep-level buffer traps. Finally, 2D device simulation is used to probe the physical insight into failure mechanisms.