Abstract
Electrostatic Discharge (ESD) has become one of the most critical reliability issues in integrated circuits (ICs). The number of circuit design iteration due to electrostatic discharge (ESD) failures increases with the complexity of VLSI technologies and their shrinking. In this paper, we show how TCAD simulation and ESD macro-model can be used to solve ESD protection issues in GGNMOS (Gate-Grounded NMOS) technology. A macro-model for ESD circuit simulation with only fitting parameter proposed. This system of model equations can capture most of the physical phenomena of the heat generation and conduction inside nano-scale devices with moderate numerical complexity. It is anticipated that the modeling concepts developed in this research may be applied in future ESD simulation studies.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
