ESD challenges in advanced CMOS systems on chip

Abstract

State-of-the-art Systems on Chip (SoC) for mobile phone applications integrate on one single chip the digital baseband core with analog blocks like power management unit, RF transceiver and mixed-signal sub-circuits. Performance considerations in such complex SoC designs include the use of ESD sensitive circuit topologies, such as thin oxide devices directly connected to I/O pads or implemented within high voltage domains, which both create new ESD challenges in advanced CMOS technology nodes. Based on 65 nm CMOS SoCs, we summarize known ESD challenges and unveil hidden issues. While advanced CMOS technology nodes already present very delicate environments with an extremely narrow window for ESD design, CDM discharge currents reach 5 to 10 A due to increased chip area. Different ESD protection concepts for a low noise amplifier (LNA) are compared where the RF-input pin connects directly to a thin oxide gate. Very-fast TLP results are correlated to on-product CDM performance. A slow turn-on behavior under fast-transient ESD stress makes the ICs particularly sensitive. In mixed device design, thin oxide devices are used in high voltage domains for which these devices are natively not suited. Reliability is ensured by extensive precautions in circuit design such no critical voltage is exceeded. ESD results of typical mixed device topologies will be discussed by associated failure modes and a protection strategy will be developed.