Abstract
The reliability of the synchronous circuits is a critical issue due to the continuous scaling of the fabrication technology. Process, voltage, and temperature (PVT) variations increase the probability of violating the timing constraints. Different techniques are used to tolerate the variability and relax the timing of the circuits. Error recovery system using taps (ERSUT) is introduced in this brief to tolerate the PVT-variation-induced delay by detecting and tolerating the error without flushing the pipeline. The faulty critical stages, due to PVT variations, are healed by borrowing slack from the next stages. As a test case, ERSUT is applied to 16 $\times$ 16-b MAC unit (currently in fabrication using Taiwan Semiconductor Manufacturing Company (TSMC) 90-nm technology). Without flushing the pipeline, the MAC unit tolerates 20% of its clock period as an additional induced delay. The proposed approach has about 20.93% overhead of area and 25.7% overhead of power.
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