Abstract
We designed, fabricated, and demonstrated an energy-efficient ERSFQ 4-bit decoder. The first version of the decoder is designed and fabricated using HYPRES legacy 1.0-μm four-layer 4.5-kA/cm 2 process. It occupies an area of 700 μm × 1800 μm, which is to be reduced to 160 μm × 400 μm once fabricated using HYPRES's RIPPLE-2 0.25-μm six-layer process. The decoder features ±13% dc bias current operating margins and below 70-aJ energy consumption per one address select operation. We report test results of the decoder and discuss its future implementation in cryogenic random access memory devices, including magnetic memory devices.
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