Error-Rate Estimation Based on Multi-Signal Flow Graph Model and Accelerated Radiation Tests.

Wei He,Zelong Zhang,Yueke Wang,Wei Deng,Kefei Xing,Jun Xu

doi:10.1371/journal.pone.0161378

Wei He, Zelong Zhang + Show 4 more

Open Access

https://doi.org/10.1371/journal.pone.0161378

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Journal: PloS one	Publication Date: Sep 1, 2016
Citations: 1	License type: CC BY 4.0

Affiliation: National University of Defense Technology

Abstract

A method of evaluating the single-event effect soft-error vulnerability of space instruments before launched has been an active research topic in recent years. In this paper, a multi-signal flow graph model is introduced to analyze the fault diagnosis and meantime to failure (MTTF) for space instruments. A model for the system functional error rate (SFER) is proposed. In addition, an experimental method and accelerated radiation testing system for a signal processing platform based on the field programmable gate array (FPGA) is presented. Based on experimental results of different ions (O, Si, Cl, Ti) under the HI-13 Tandem Accelerator, the SFER of the signal processing platform is approximately 10−3(error/particle/cm2), while the MTTF is approximately 110.7 h.

Highlights

With the wide application of very-large-scale integration(VLSI) on space instruments, along with the decline of device feature size and rise of operation frequency, the single event effect (SEE) is becoming a serious safety problem [1, 2]
In traditional multi-signal flow graph (MSFG) model, the quantization relationship between two modules is 1 or 0, because it supposes that fault is certain and one fault can lead to another fault
Several approaches have been developed to model the SEE soft error propagation based on MSFG

Summary

Introduction

With the wide application of very-large-scale integration(VLSI) on space instruments, along with the decline of device feature size and rise of operation frequency, the single event effect (SEE) is becoming a serious safety problem [1, 2]. Multi-signal flow graph modeling can be used to check the fault mode from upper to lower levels by adding testing points and searching for the SEE vulnerability component. In this part, a typical signal processing platform which consists of typical VLSIs is introduced. The testing point is a setting in the internal position of the device, which implements the signal processing function, especially for SRAM-based FPGA and DSP. Transients are generated from the basic physical interaction of single ionizing particles with semiconductor

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Experimental Results and Discussion

Conclusion