Error-correction schemes with erasure information for fast memories

Abstract

Two error correction schemes are proposed for binary memories that can be affected by erasures, i.e. errors with known location but unknown value. The erasures considered here are due to the drifting of the electrical parameter used to encode information outside the normal ranges associated to a logic 0 or a logic 1 value. For example, a dielectric breakdown in a magnetic memory cell may reduce its electrical resistance sensibly below the levels which correspond to logic 0 and logic 1 values stored in healthy memory cells. Such deviations can be sensed during memory read operations and the acquired information can be used to boost the fault masking capacity of an error-correcting code. Here, we investigate the use of erasure information to enable double-bit error correction with the help of single-bit error correction and double-bit error detection codes or shortened single-bit error correction codes.