Error-Vulnerable Pattern-Aware Binary-to-Ternary Data Mapping for Improving Storage Density of 3LC Phase Change Memory

Jeong Beom Hong,Yong Wook Kim,Tae Hee Han,Young Sik Lee

doi:10.3390/electronics9040626

Abstract

Multi-level cell (MLC) phase-change memory (PCM) is an attractive solution for next-generation memory that is composed of resistance-based nonvolatile devices. MLC PCM is superior to dynamic random-access memory (DRAM) with regard to scalability and leakage power. Therefore, various studies have focused on the feasibility of MLC PCM-based main memory. The key challenges in replacing DRAM with MLC PCM are low reliability, limited lifetime, and long write latency, which are predominantly affected by the most error-vulnerable data pattern. Based on the physical characteristics of the PCM, where the reliability depends on the data pattern, a tri-level-cell (3LC) PCM has significantly higher performance and lifetime than a four-level-cell (4LC) PCM. However, a storage density is limited by binary-to-ternary data mapping. This paper introduces error-vulnerable pattern-aware binary-to-ternary data mapping utilizing 3LC PCM without an error-correction code (ECC) to enhance the storage density. To mitigate the storage density loss caused by the 3LC PCM, a two-way encoding is applied. The performance degradation is minimized through parallel encoding. The experimental results demonstrate that the proposed method improves the storage density by 17.9%. Additionally, the lifetime and performance are enhanced by 36.1% and 38.8%, respectively, compared with those of a 4LC PCM with an ECC.

Highlights

Multi-level-cell (MLC) phase-change memory (PCM) has the potential to replace dynamic random-access memory (DRAM) in the main memory owing to its excellent device down-scaling and standby power consumption characteristics [1,2]
We propose an error-vulnerable pattern-aware parallel data encoding method to address the storage density reduction associated with 3LC PCM-based main memory
The remainder of this paper is organized as follows: We review the background of MLC PCM

Summary

Introduction

Multi-level-cell (MLC) phase-change memory (PCM) has the potential to replace dynamic random-access memory (DRAM) in the main memory owing to its excellent device down-scaling and standby power consumption characteristics [1,2]. The MLC PCM stores multiple bits in a single cell using the wide variable-resistance characteristic of the GST (Ge2 Se2 Te5 ) material, which changes its physical state when a current pulse is applied. MLC PCM stores multiple bits per cell by dividing the wide resistance spectrum of a GST. MLC PCM stores multiple bits per cell by dividing the wide resistance spectrum of a GST material. As the proportion of amorphous states in the PCM cell increases, the resistance value. As the proportion of amorphous states in the PCM cell increases, the resistance value increases. In the case of a single-level-cell (SLC), 1-bit data can utilize the resistance values that differ by RESET generates a short and high-power current pulse to data writing operations, RESET generates a short and high-power current pulse to form an amorphous form an amorphous state with high resistance, and SET produces a crystalline state with low state with high resistance, and SET produces a crystalline state with low resistance by applying low resistance by applying low power for a relatively long time [22,23].

Methods

Results

Conclusion