Error suppressing encode logic of FCDL in a 6-b flash A/D converter

Abstract

A 6-b, 166-Ms/s BiCMOS flash A/D converter was fabricated using a folded cascoded differential logic (FCDL). This FCDL reduces glitch errors caused by comparator metastability and improves encoder operation speed. The measured error rates of a chip implemented in a 0.7-/spl mu/m, f/sub t/=12 GHz BiCMOS was less than 10/sup -10/ times/sample. Without power-consuming highspeed track and hold circuit, the FCDL achieved low error rate and low power consumption of 505 mW at a 5.0-V power supply.