Error Floor Investigation and Girth Optimization for Certain Types of Low-Density Parity Check Codes

Abstract

Low-density parity check (LDPC) codes with their near-Shannon capacity limit error correcting performance and iterative decoding algorithm are being evaluated for digital communications applications. For LDPC codes to be used in real systems, their error floors need to be investigated. In this paper, we evaluate the performance of disjoint difference set (DDS)-based LDPC codes (with column weights 3, 4, 5) and array code-based LDPC codes (with column weights 3, 4, 5) in the additive white Gaussian noise (AWGN) channel using a high-speed field programmable gate array (FPGA) simulation platform. The error floor regions (bit error rates down to 10/sup -12/) of those codes are presented. For better performance of array codes, a girth optimization method is proposed and the FPGA evaluation results are presented.