Abstract
On-chip error correction for random-access memories is not very popular because of the high overhead necessary. This paper presents a technique that performs a single-bit correction and a double-bit detection on clocked memories where all column data is internally available, with an area penalty of less than 20 percent. The timing overhead for on-chip implementation is less than the time required to generate a parity bit. The detection and correction operation is transparent to the user and does not require different cycle times for the detection and the correction.
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