Abstract
An error-correction technique for monolithic high-speed A/D and D/A converters, based on binary weighted capacitor arrays, is introduced. Each capacitor in the array has its individual calibration capacitor and voltage source. The calibration voltages are generated by resistive DACs. An N-bit converter requires N additional capacitors, N analog switching matrices, and N bytes of memory space. The error-acquisition technique and practical design considerations are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
