ERCCL: energy recovery capacitance coupling logic

Abstract

The non-adiabatic loss of ERCCL is independent of the size of the associated circuit and the load capacitance; it depends only on the gate count in the circuit. ERCCL does not implement logic through a switch logic network but through capacitance coupling, which decrease its turn-on resistance and adiabatic loss. ERCCL not only reduces dissipation at the circuit level, but also its loss and performance can be optimized further through choosing a threshold logic topology at the architecture level. A 4-bit ERCCL adder is designed, and 4-bit 2N-2N2P and static CMOS adders are designed for comparison. Layout-based simulation with CSMC 0.6 /spl mu/m DPDM technology shows that the dissipation of the ERCCL circuit is only 50% of that of the 2N-2N2P circuit, and 28-41% of that of the static CMOS circuit.