ER

Abstract

Phase Change Memory (PCM) has recently emerged as a promising nonvolatile memory technology. To effectively increase memory capacity and reduce per bit fabrication cost, multi-level cell (MLC) PCM stores more than one bit per cell by differentiating multiple intermediate resistance levels. However, MLC PCM suffers from significantly shortened endurance due to its large RESET current that initiates the cell state. In this paper, we propose elastic RESET (ER) to construct non-2n-state MLC PCM, e.g., 3-state MLC PCM instead of 4-state one for 2-bit MLC. We then adopt data compression and propose fraction encoding to store compressed data using non-2n-state MLC. By reducing RESET energy, ER significantly reduces write power and prolongs PCM lifetime. On average, we observed 17% RESET power reduction and 32x endurance improvement for 2-bit MLC.