Abstract
The need for low-resistance, shallow contacts in Si-based microelectronic devices has driven the search for fabrication techniques of epitaxial silicides which are compatible with the manufacturing environment. For ultra large scale integration (ULSI) applications, techniques such as high temperature sputtering (HTS), Ti-interlayer mediated epitaxy (TIME), and oxide mediated epitaxy (OME) have shown varied degrees of success, and also problems. In this paper, a number of modifications aimed at simplifying the OME technique will be presented. New experimental results regarding HTS on sloped Si surfaces will also be described which suggest possible improvement to the HTS technique.
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