Environmental Effects on Dielectric Films in Plastic Encapsulated Silicon Devices

Abstract

Mechanical integrity of interlayer and intralayer dielectric films and its impact on interconnect reliability has become more important as critical dimensions in ultralarge-scale integrated circuits are continuously reduced and Cu interconnect, low-k dielectrics (Cu/low-k) are widely adopted for the new technology nodes. Mechanical integrity of the dielectric films and reliability of interconnect can be affected by the film deposition process, stresses from chip-packaging interaction (CPI) and environmental factors such as moisture and temperature exposure. In this study attention has been focused on understanding the moisture and temperature effects on reliability of dielectric films in plastic encapsulated silicon devices. Sensitivities to moisture and temperature induced damage in the dielectric films of the silicon devices were first evaluated using accelerated temperature and humidity stress conditions. Multiple stress conditions were used so the testing results could be applied to validate a physical acceleration model for the combined temperature and humidity stresses. Moisture diffusion in the silicon devices and their packages was then modeled using commercial finite element analysis (FEA) software. Moisture sorption and diffusion properties of the packaging materials were also characterized to support the moisture diffusion modeling. Moisture distribution in the plastic package was analyzed for both the accelerated stress conditions and the product use or storage environmental conditions. The effectiveness of the peripheral seal ring on the silicon device as a moisture barrier was also investigated. Finally, reliability of the silicon devices under typical and extreme product use or storage environment conditions was assessed using the moisture distribution results and the validated acceleration model.