Enhancing the cooling performance of thermocouples: a power-constrained topology optimization procedure

Abstract

Heat pumping through thermoelectric devices has many advantages over traditional cooling. However, their current efficiency is a limiting factor in their implementation. In this paper, we approach the non-convex topology optimization of thermoelectrical elements for cooling applications through the method of moving asymptotes (MMA) to improve their cooling capabilities per watt usage. The optimization problem is defined for a given power budget, aiming for the minimum temperature with a known heat pumping need. The introduction of power as a constraint justifies the introduction of the voltage gradient across the thermocouple as a design variable to maintain the thermoelectrical device in its optimum power-to-heat extraction ratio. To better understand the convergence of this non-convex problem, we present a two-variable analytical thermoelectric optimization model. This example provides information on how to select the penalty parameters used to scale the three material coefficients involved in the problem to obtain lower objective values and better convergence using MMA. The analytical model shows the non-convexity of the problem and provides the recommendation to use penalization coefficients of the form pk=pσ>pα=1\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$p_k=p_{\\sigma }>p_{\\alpha }=1$$\\end{document} for the thermal conductivity, electrical conductivity, and Seebeck coefficients. We tested these penalization coefficients through optimizations of a model based on the 1MC10-031 commercial thermoelectric-cooler (TEC) using the finite element method (FEM). These penalization coefficients provided local minima without the need for volume constraints. With this procedure, we found designs that provided temperatures close to 10 degrees lower using 60% less semiconductor material volume compared to the initial design.