Enhancing system-wide power integrity in 3D ICs with power gating

Abstract

Power gating is a commonly used method to reduce subthreshold leakage current in nanoscale technologies. In through silicon via (TSV) based three-dimensional (3D) integrated circuits (ICs), power gating can significantly degrade system-wide power integrity since the decoupling capacitance associated with the power gated block/plane becomes ineffective for neighboring active planes, as demonstrated in this paper. A reconfig-urable decoupling capacitor topology is investigated to alleviate this issue by exploiting the ability of via-last TSVs to bypass plane-level power networks when delivering the supply voltage. Reconfigurable decoupling capacitors placed within a plane can provide charge to neighboring planes even when the plane is power gated, thereby significantly reducing both RMS power supply noise (by up to 46%) and RMS power gating (in-rush current) noise (by up to 85%) at the expense of a slight increase in area (by 1.55%) and peak power consumption (by 1.36%).