Enhancing switching threshold for wide fan-in domino gates with shortened evaluation period

Abstract

With technology scaling up, noise resistance has become critical in high performance VLSI chips using wide fan-in domino gates. Techniques for enhancement of noise tolerance in domino gates incur cost in terms of design metrics like power dissipation, delay and die area. Existing techniques improve noise immunity of domino gates either by precharging the internal node of PDN or controlling the evaluation period. Pre-charging the internal nodes increases switching threshold of the evaluation transistors and demands more transistors leading to overheads not desirable for wide fan-in gates. Controlling the evaluation period of clock provides protection against noise pulse duration only. In this paper, we present an approach that combines two techniques to protect the circuit against magnitude as well as width of a noise pulse in an effort to enhance the overall noise immunity of wide fan-in domino gates. Simulation results show that our technique increases noise immunity significantly. Validation of our approach in presence of PVT variations demonstrates suitability of the proposed technique for wide fan-in gates implemented in deep sub-90 nm technology.