Abstract
With the rapid development of the Internet-of-Things (IoT), sensors are being widely applied in industry and human life. Sensor networks based on IoT have strong Information transmission and processing capabilities. The security of sensor networks is progressively crucial. Cryptographic algorithms are widely used in sensor networks to guarantee security. Hardware implementations are preferred, since software implementations offer lower throughout and require more computational resources. Cryptographic chips should be tested in a manufacturing process and in the field to ensure their quality. As a widely used design-for-testability (DFT) technique, scan design can enhance the testability of the chips by improving the controllability and observability of the internal flip-flops. However, it may become a backdoor to leaking sensitive information related to the cipher key, and thus, threaten the security of a cryptographic chip. In this paper, a secure scan test architecture was proposed to resist scan-based noninvasive attacks on cryptographic chips with boundary scan design. Firstly, the proposed DFT architecture provides the scan chain reset mechanism by gating a mode-switching detection signal into reset input of scan cells. The contents of scan chains will be erased when the working mode is switched between test mode and functional mode, and thus, it can deter mode-switching based noninvasive attacks. Secondly, loading the secret key into scan chains of cryptographic chips is prohibited in the test mode. As a result, the test-mode-only scan attack can also be thwarted. On the other hand, shift operation under functional mode is disabled to overcome scan attack in the functional mode. The proposed secure scheme ensures the security of cryptographic chips for sensor networks with extremely low area penalty.
Highlights
In recent years, Internet-of-Things (IoT) has developed rapidly; it connects various objects around the world through the internet
After encryption algorithm is implemented in cryptographic chip for one round during functional mode, the intermediate encryption results are stored in scan chains
A certain number of clock pulses are applied to ShiftClock of each boundary scan cell (BSC) and clock input of each regular scan cells (RSC) such that a test vector can be scanned serially into the scan chains via the scan-input pins
Summary
Internet-of-Things (IoT) has developed rapidly; it connects various objects around the world through the internet. After encryption algorithm is implemented in cryptographic chip for one round during functional mode, the intermediate encryption results are stored in scan chains If permitted, at this time the adversary may switch the circuit into test mode to shift out the intermediate states by scan operation and observe at the output ports of scan chains. The adversary first resets the chip to an initial state He applies the pre-calculated test vectors (i.e., plaintexts) to cipher module and capture intermediate encrypted result into scan chains in functional mode. We propose a secure scan scheme to protect cryptographic chips with symmetric key in sensor networks against scan-based attacks. The proposed technique is demonstrated on AES chips but can be extended to cryptographic chips with symmetric key
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
