Enhancing Data Security using Obfuscated 128-bit AES Algorithm - An Active Hardware Obfuscation Approach at RTL Level

Abstract

Nowadays, integrated circuits (ICs) security grown as a primary responsibility at every stage of IC supply chain due to the globalized design, fabrication, test, deployment and monitoring of an IC. In this regard, Advanced Encryption Standard (AES) is widely accepted and supported in both the domain, software as well as hardware. To diminish the effect and cause of different threats, researchers identified that the hardware obfuscation based AES is a promising technique and a solution towards piracy and reverse engineering. This paper discusses about the design and simulation of 128-bit AES algorithm using active hardware obfuscation techniques. 128-bit AES is designed and simulated using Xilinx Vivado 2016.2. In this paper simulation results of 128-bit AES algorithm are analyzed with and without obfuscation techniques. Results shows that with obfuscation techniques 128 bit AES algorithm offer higher level of security and implementation flexibility with small area overhead and power overhead. The robustness of proposed algorithm is also analyzed in the form of throughput and efficiency. The authors also presented the power consumption and analyzed the area overhead of proposed algorithm with different xilinx 7 -series FPGAs.