Enhancements in Deterministic BIST Implementations for Improving Test of Complex SOCs

Abstract

Innovative solutions have been proposed to reduce the test cost of SOC designs. STUMPS (self-test using PRPG and MISR structures) architecture based logic BIST (built-in self-test) is one such popular solution which attempts to reduce the cost of scan based tests by exploiting shorter scan chains in the design. To address the lower test coverage attainable through traditional random pattern logic BIST, several enhancements have been proposed. Deterministic BIST based on periodic re-seeding is one such. This paper discusses various enhancements that have been implemented in deterministic BIST, (using DBIST from SOC-BIST test suite from Synopsys Inc.), on recent complex SOC designs in Texas Instruments (India). These include (i) controller support for internal high speed shift and self-test, (ii) programmable solution for dynamic handling of Xs, (Hi) clock control methodology for reduced pattern volume of at-speed tests across multiple clock domains, and (iv) efficient diagnostics using DBIST patterns. Experimental results are presented on various designs where these features have been implemented, to illustrate the positive impact on test cost as well as test quality