Enhancement of Night Time Video using Dark Channel Prior IP Accelerator

Rakotojaona Nambinina,Microelectronics, University Of Mons, Mons, Belgium ,Haresh Suthar,Yogesh Parmar,C Valderrama,Ece, Parul University, Vadodara, India

doi:10.35940/ijeat.d6707.049420

Rakotojaona Nambinina, Microelectronics, University Of Mons, Mons, Belgium + Show 4 more

Open Access

https://doi.org/10.35940/ijeat.d6707.049420

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Abstract

The enhancement of night-time video using Dark Channel Prior IP accelerator is proposed in this paper. Night time video processing is difficult due to low brightness, low contrast and high noise in the video. The above problems affect the accuracy and may results in failures of object detection in night time video. Dark Channel Prior (DCP) filter is used to improve the visibility, brightness and contrast of the video at night time. Processing speed is challenging task on real time application of DCP algorithm for night time video enhancement. Hence, DCP algorithm is implemented on FPGA (ALVEO Board) to increase the speed of video processing.

Highlights

Object detection in real time video is one of the prevalent applications in the field of video processing
Dark Channel Prior (DCP) algorithm can be implemented on hardware using general purpose microprocessor, or graphics processing unit (GPU) or on FPGA
Mean square error (MSE): MSE measures the average of the square errors, if x(i,j) is the source images with M and N are the number of rows and columns of the source images, And Y, the reconstructed by decoding the encoded version of x(i,j) The mean square error is defined by the equation (6) bellow: (6)

Summary

INTRODUCTION

Object detection in real time video is one of the prevalent applications in the field of video processing. The algorithms are required to be accelerated for object detections in real time video. DCP algorithm can be implemented on hardware using general purpose microprocessor, or graphics processing unit (GPU) or on FPGA. If users are looking to move into the generation technology Vitis application acceleration development flow is the latest in Xilinx FPGA-based software acceleration. An application acceleration flow, and use of the Vitis core development kit and Xilinx Runtime is provided [2]. The new tool provides framework as caffe tensor flow for developing an application on FPGA. In Vitis software the application program is split into host and kernel. The both software and hardware can be used as high-level programming using C++ for hardware acceleration.

RELATED WORK

Design flow of night time enhancement based DCP algorithm

Performance parameter

RESULT

CONCLUSION