Enhancement of hot-carrier injection resistance for deep submicron transistor gate dielectric with a powered solenoid

Abstract

The operational reliability of ultrathin gate dielectrics in forthcoming metal–oxide–semiconductor field-effect transistors (MOSFETs) will be impaired if there is the occurrence of hot-carrier injection (HCI) into the gate across the gate dielectric. In this work, a method is proposed to mellow the undesired effects incurred by HCI in a n-type MOSFET (NMOSFET) via a reduction in its frequency. The method involves the powering of a polycrystalline silicon (polysilicon) solenoid at the same time when the gate and drain of transistors are powered. The localized magnetic field generated from the solenoid can impose a downward force (Hall effect) to counteract or compensate the upward driving force exerted on the energetic electrons reaching the drain by the applied gate voltage. Fewer electrons will be trapped and the quality, reliability, and lifetime of the device will improve as a consequence.