Enhancement-Mode Buried Strained Silicon Channel Double Quantum Dot with Integrated Electrometer

Abstract

We proposed and demonstrated an enhancement-mode SiGe/strained-Si stack for a quantum dot [1], which both spaces the quantum dot away from interface defects and removes dopants. Smooth and predictable potentials for single electron quantum dots are highly desirable for beyond Moore's law approaches like quantum annealing and quantum computing. Enhancement-mode SiGe/sSi field-effect transistors (FETs) have been demonstrated previously [2,3] and have recently achieved mobilities as high as 1.6x106 cm2/V s [4], indicating that a smooth potential approaching other model systems like GaAs can be produced in Si. This material stack has subsequently been used successfully by a different group to produce coherent qubit spin rotations [5]. We report in this letter that low-disorder quantum dots can be formed using a double-top-gated lateral quantum dot nanostructure, defined using 180 nm line width platform and fabricated in a 150 mm wafer batch-processing tool set in the Sandia National Labs silicon foundry. This is an important step towards showing that defects, lithography and process tolerances in a Si foundry are sufficient to build low disorder double quantum dots for both quantum computing and quantum annealing.