Enhanced Via Integration Process for Copper/Ultralow- $k$ Interconnects

Abstract

This letter evaluates the electrical and reliability performances of a back-end-of-line Cu/ultralow- k (ULK) dielectric interconnect with features of gouged via and damage-free profile. The interconnect structure in ultralarge-scale integrated circuits forms vias between successive layers by forming first the via opening within the ULK dielectric, followed by forming the via-gouging feature and then the line opening. This fabrication approach does not disrupt the coverage of the deposited trench diffusion barrier in a line opening and does not introduce dielectric profile damages caused by creating the via-gouging feature. The resulting interconnect structure maintains the gouged-via feature without any profile damage, which not only improves the overall integrity of the integrated circuit but also shows time-dependent dielectric-breakdown performance enhancement over the conventional interconnect structure.