Enhanced stress-migration reliability for ULSI interconnect: An insight into the perils of screening Al depositions based on grain size

Abstract

The recent trend toward increasing packing density and the demand for improved reliability have dramatically challenged ultra large scale integrated circuit technologists to develop more robust fabrication processes. Finer feature sizes and the addition of layers of interconnect, combined with large mechanical stresses, have greatly exacerbated the insidious problem of stress-induced voiding—open circuits can appear in Al lines immediately after fabrication or after years of shelf storage. Finite element analysis shows that one of the prime candidates for controlling the root cause of the failure mechanism, stress-assisted grain-boundary diffusion, is carefully engineered Al grain size. This paper examines various parameters related to grain size that directly result in mechanically weak populations of interconnect elements. We highlight some critical factors that give rise to unique implementation issues, including the complex statistical nature of the susceptible sites and the evolution of the microstructure during device fabrication. The resulting experimental reliability enhancement can be startling—a new deposition process accounted for a 350% increase in lifetime in sub-micron wide lines.