Enhanced pin-access prediction and design optimization with machine learning integration

Abstract

In daily increasing integrated circuit complexity, standard cell pin accessibility is becoming more significant part of design process. As pin density is increasing, fast and efficient algorithms for pin-access prediction and optimization are needed. However current methods do not ensure the best trade-off between DRV count decrease and tool runtime optimization.In this paper pin accessibility checking and optimization method is proposed, which is using machine learning algorithms to increase accuracy of pin-access predictions and decrease DRV count. Results show that with using proposed method, DRV count can be decreased by 47%, while having increase in runtime by 23%.