Enhanced Performance of Strained Graphene Wrapped Channel Cylindrical FET

Abstract

In order to perform logic and memory operation with high speed and accuracy, transistors should have high ON/OFF current ratio and high charge carrier mobility. But it is difficult to achieve both of these criteria in a single transistor. Graphene is considered as one of the most promising candidates due to its high mobility. But graphene field effect transistor (GFET) gives very low ON/OFF current ratio as graphene is a semi-metallic material. In this work, we have modeled strained graphene on silicon FET with high k dielectric material like HfO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> , TiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> and obtained notable improvement in the ON/OFF current ratio along with the drain current. But the structure suffers from significant channel length modulation effect. Finally, we have proposed a cylindrical FET structure with strained graphene layer to minimize the channel length modulation effect while maintaining the high ON/OFF current ratio and high charge carrier mobility.