Enhanced integrated injection logic performance using novel symmetrical cell topography

Abstract

Contemporary I <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> L logic gate structures use an in-line topography for the multiple collector npn transistor. Decoupling effects between adjacent segments introduce a spread in the relative performance of the outputs with respect to gain, maximum collector current, and propagation delay. A novel cell layout, which enables the base contact and pnp injector to be symmetricaUy positioned relative to every collector in a multiple collector device, was developed. In controlled experiments, using an industry compatible fabrication process, symmetrical quad output cells demonstrated a factor-of-20 increase in the magnitude of useful npn collector current and the degree of gain uniformity among outputs.