Enhanced Hot-Hole Induced Degradation of Strained p-Channel Metal Oxide Semiconductor Transistors in Complementary Metal Oxide Semiconductor Technology with 2.0 nm Gate Oxide

Abstract

The effects of process-induced strain silicon (PSS) technology on hot-hole induced degradation of p-channel metal oxide semiconductor (PMOS) transistors using 2.0 nm ultra-thin nitrided gate oxides will be reported. An understanding of the effects of strain on hot-hole induced degradation will be very important for sub-65 nm complementary MOS (CMOS) technology since PSS technology was said to be a preferred approach to strain transistors. It was discovered that as source drain diffusion length (Lov) decreased, which then gave rise to high compressive strain (HCS) in the channel region of the PMOS transistor, hot-hole induced degradation was enhanced. The improved direct-current current–voltage (IDCIV) method, which allows us to characterize both interface traps (Nit) and oxide charge traps (Not) generation, suggested that no additional interface trap (ΔNit) generation was created when the strain profile of the channel was changed. However, it was observed that positive charge trappings or slow states was enhanced in HCS PMOS transistors which would lead to enhanced hot hole induced degradation after long term stressing.