Enhanced design and hardware implementation of a chaos-based block cipher for image protection

Abstract

Nowadays chaos-based cryptography systems are widely used to protect sensitive data. A variety of chaos-based cryptosystems with software implementation has been published in the literature. However, due to the rapid growth of connected devices, the development of hardware secure and low-resource cryptographic systems is necessary. In this paper, we enhance the design of one of our software cryptosystems and then we address its FPGA-based implementation. The improvement in the design consists essentially to introduce an Initial Vector (IV) entry to the Chaotic Pseudo Random Number Generator (CPRNG) thus allowing to generate a new dynamic keys for the confusion layer (using a modified 2-D cat map) and diffusion layer (using a logistic map) with each new execution of the system. The CPRNG is formed by XORred a discrete Skew Tent Map (STM) with a discrete Piecewise Linear Chaotic Map (PWLCM). The proposed cryptosystem, which operates in Cipher Block Chaining (CBC) mode, is controlled by a Finite State Machine (FSM) to ensure that both the encryption and decryption are performed by the same reconfigurable architecture. The system is implemented on a Xilinx XC7Z020 ZYNQ FPGA platform. The results obtained in terms of hardware implementation costs (logic resources, throughput, and efficiency) and in terms of security against cryptographic attacks demonstrate the effectiveness of the proposed chaos-based cryptosystem.