Enhanced computation method of topological smoothing on shared memory parallel machines

Ramzi Mahmoudi,Mohamed Akil

doi:10.1186/1687-5281-2011-16

Abstract

To prepare images for better segmentation, we need preprocessing applications, such as smoothing, to reduce noise. In this paper, we present an enhanced computation method for smoothing 2D object in binary case. Unlike existing approaches, proposed method provides a parallel computation and better memory management, while preserving the topology (number of connected components) of the original image by using homotopic transformations defined in the framework of digital topology. We introduce an adapted parallelization strategy called split, distribute and merge (SDM) strategy which allows efficient parallelization of a large class of topological operators. To achieve a good speedup and better memory allocation, we cared about task scheduling and managing. Distributed work during smoothing process is done by a variable number of threads. Tests on 2D grayscale image (512*512), using shared memory parallel machine (SMPM) with 8 CPU cores (2× Xeon E5405 running at frequency of 2 GHz), showed an enhancement of 5.2 with cache success rate of 70%.

Highlights

Smoothing filter is the method of choice for image preprocessing and pattern recognition
Objects are defined as sets of grid points, and topology preservation is ensured by the exclusive use of homotopic transformations defined in the framework of digital
We have presented a new parallel computation method for topological smoothing through combining parallel computation of Euclidean Distance Transform using Meijster algorithm and parallel Thinning-Thickening processes using an adapted version of Couprie’s algorithm

Summary

Introduction

Smoothing filter is the method of choice for image preprocessing and pattern recognition. 4.3.1 Execution time We implemented two versions of the proposed parallel topological smoothing algorithm, the first one using ‘Symmetric Multiprocessing’ scheduler and the second one using ‘basic-NPS’ scheduler. For the second implementation, using our scheduler, the speedup has increased to 5.2 ± 0.01 Another common result between different architecture is stability of execution time on each n-core machine since the code uses n or more threads. New approaches to reduce cache miss are developed such as taking advantage of locality of references to memory or using aggressive multithreading so that whenever a thread is stalled, waiting for data, the system can efficiently switch to execute another thread This is because as more instructions are available for each memory access, fewer threads are needed to fill the stall time resulting from waiting for memory

Conclusion

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