Enhanced analog performance of doping-less dual material and gate stacked architecture of junctionless transistor with high-k spacer

Abstract

The potential effectiveness of high-k spacer for the enhanced analog performance of doping-less dual material double-gate (DL-DMDG) junctionless transistor (JLT) is proposed. The impact of gate stacked (GS = SiO2 + high-k) architecture on DL-DMDG is also demonstrated. The charge plasma technique is used to form n + source/drain in an intrinsic silicon film by proper selection of source/drain electrode work function. The analog parameters are analyzed for DL-DMDG JLT with high-k spacer (DL-DMDG-HK) and gate stacked architecture of DL-DMDG-HK (DL-GSDMDG-HK). The results are compared with DL-DMDG JLT and its gate stacked architecture (DL-GSDMDG) JLT. The DL-DMDG-HK JLT shows improved electrostatic integrity with enhanced on-state current, transconductance (g m), early voltage (V EA) and intrinsic gain (A V ) as compared to DL-DMDG and DL-GSDMDG-JLTs. Moreover, DL-GSDMDG-HK further enhances these figures of merits (FOMs).