Enhanced 2-DPR Replacement Algorithm

Abstract

Caching is a common term used in many systems to maximize the performance of the system such as a web cache. This concept has been utilized in processor’s speed to lower the latency of fetching data from the main memory throw system bus long way to the processor. Cache Miss and Cache Hit is main events occurred when any block is being referenced by the processor from cache. Replacement algorithm works to make the decision to evict the block when Cache Miss occurred, as well as, increase the possibility of keeping block when Cache Hit occurred. The objective of replacement algorithm is to utilize the cache memory as efficient as possible with limit size of cache to minify cache miss and maximize the cache hit to get better efficiency for the system. Two-Dimensional Pyramid Replacement algorithm, (2-DPR), is an algorithm that combines the advantages (LRU) Least Recently Used and (LFU) Least Frequently Used (LRU) , and eliminates their disadvantages. The problem of this algorithm is giving high performance, low complexity, implementable in hardware, but not high hit ratio. In this paper, an enhanced method of 2-DPR is used to take advantage of Low Inter-reference Recency Set (LIR) to calculate the distance between the last referenced index and the current reference index in the cache by setting a counter called Inter-Reference Recency (IRR) in each block. By this method, we are attempting to gain high performance and high hit ratio.