Abstract
The architecture of multipath delay commutator (MDC) and memory scheduling are the basic concepts used to implement fast Fourier transform (FFT) processors with variable length. These FFT processors are used in orthogonal frequency division multiplexing systems, having multiple number of inputs and multiple number of outputs. Depending on this MDC architecture, we implement the fft/ifft processor based design which is proposed in this paper. In this design we implement ram, fifo, input buffer and output sorting buffer. The functionality verification and the synthesis is carried out using XILINX ISE 12.3i and shows the reduced delay values.
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