Abstract
The full adder design is based upon the split path data driven dynamic logic (PROPAGATE and GENERATE).The adders were characterized for their performance and power consumptions when operated on different supply voltages and fan-outs. This paper involves the reduction in the leakage current and power consumption in the circuit. The static leakage power dissipations can be reduced by supply voltage gating technique which can be done through the transistor, placed between Vdd /Gnd rail and the circuit. This allows the supply voltage to flow through the circuit only during the needed time .As the transistor becomes ON condition then only the power is applied to the circuit. By this method the static power gets reduced and the speed of the process also improved with high drivability with comparing to the conventional dynamic domino adders. By this technique of reducing the leakage power, the expecting power consumption is about 30% less than the existing method .Thus the newly designed full adder with reduced power consumption is implemented in the array multiplier for better performance.
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