English

Abstract

The main purpose of VLSI placement is to place the objects into fixed chip such that there should be no overlaps among the objects and some cost metric such as wire length and routability is optimized. Physical synthesis optimizations and changing the placement method typically change the locations of cells, resize cells or add more cells to the design after global placement. But, those changes generally leads to wire length increases; thus another method of optimizations to for further improve wire length, timing and routing congestion characteristics is required. The Incremental Detailed Placement techniques could be useful in this condition. So, we propose a new detailed placement paradigm, which use a set of pin-based timing and electrical constraints in detailed placement to prevent it from degrading timing or violating electrical constraints while reducing wire-length.