Abstract
Memristor devices have been extensively studied as one of the most promising technologies for next-generation non-volatile memory. However, for the memristor devices to have a real technological impact, they must be densely packed in a large crossbar array (CBA) exceeding Gigabytes in size. Devising a selector device that is CMOS compatible, 3D stackable, and has a high non-linearity (NL) and great endurance is a crucial enabling ingredient to reach this goal. Tunneling based selectors are very promising in these aspects, but the mediocre NL value limits their applications in large passive crossbar arrays. In this work, we demonstrated a trilayer tunneling selector based on the Ge/Pt/TaN1+x/Ta2O5/TaN1+x/Pd layers that could achieve a NL of 3 × 105, which is the highest NL achieved using a tunnel selector so far. The record-high tunneling NL is partially attributed to the bottom electrode's ultra-smoothness (BE) induced by a Ge/Pt layer. We further demonstrated the feasibility of 1S1R (1-selector 1-resistor) integration by vertically integrating a Pd/Ta2O5/Ru based memristor on top of the proposed selector.
Highlights
crossbar array (CBA) was proposed and adapted for telecommunication switching systems at the beginning of the twentieth century (Craft, 1925)
Since readout current for low resistance state (LRS) is larger than high resistance state (HRS), LRS current is only mildly affected by the sneak path current and so does the LRS resistance state
We developed a Ge/Pt/TaN1+x/Ta2O5/TaN1+x/Pd based trilayer tunneling barrier (TLTB) selector, which combined the benefit of a staircase potential barrier with the smooth bottom electrode’s ultra-smoothness (BE)
Summary
CBA was proposed and adapted for telecommunication switching systems at the beginning of the twentieth century (Craft, 1925). A control sample with the same TLTB structure but on different BE layers, i.e., Ti/Pt, showed a NL of about 100, as shown in Supplementary Figure 6, which indicates the importance of using a smooth BE for tunneling selector devices. It is worth noting that in this vertically integrated 1S1R cell, the selector was deliberately placed at the bottom to exploit the smooth BE (Ge/Pt) for achieving a high NL We designed this testing structure in a way that the ME can be electrically accessed so that measurements can be made on the “1S1R” cell and on the individual “S” and “R” to better understand the device stack. Since readout current for LRS is larger than HRS, LRS current is only mildly affected by the sneak path current and so does the LRS resistance state
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