Engineering the III-V Gate Stack Properties by Optimization of the ALD Process

Abstract

The passivation of the interface between the IIIV substrate and the high-k is key in order to bring these materials into the 7nm technology node. A high amount of interface states (Dit>1E13 /cm2eV) will trap the electrons resulting in a reduced mobility and degraded subtreshold slope[1]. Additional defects present in the oxide near the IIIV interface will generate device instabilities[2]. The goal should be to reduce the amount of oxide traps below 1.5E10/cm2at an operating field of 3.5E6 V/cm in order to meet the 10 years reliability target. In this paper, it will be shown that careful engineering of the ALD process can yield a high quality interface at low CET values (<1.5nm). However, the bulk oxide trapping behavior is not changed accordingly with the ALD process and further improvement is required.TMA prepulsing, H2S exposure as well as the incorporation of a thin ALD rare earth (RE) oxide layer have been studied as a way to reduce the Dit level at the In0.53Ga0.47As/high-k interface. In addition, we present the oxide trap behavior for these different pretreatment/high-k combinations.TMA prepulsing has been reported to improve the interface quality of the In0.53Ga0.47As/ high-k interface[3]. We have studied the influence of the TMA pulse length in combination with ALD Al2O3 (TMA/H2O), HfO2 (HfCl4/H2O) and AlSiOx (TMA based and C-free process). For a 4nm Al2O3 layer, an optimal Dit is obtained when the TMA pulse length is increased from the standard 0.1 s up to 5 s during the first 5 ALD cycles (Figure 1). For a higher number of cycles with long TMA pulses, the Dit level increases again. This could be attributed to the increase of unreacted –CH3 groups as the H2O pulses were kept the same as compared to the standard TMA pulse length. Similar behavior can be found with a 4nm HfO2 stack: pretreatment of the interface with 5 cycles (TMA/H2O purge) with a 5s TMA pulse lowers the Dit by a factor ~2 compared to no pretreatment.The idea of using AlSiOx is to slow down the oxide trap response because of a possible higher Ec offset to the InGaAs channel. The incorporation of Si into the Al2O3 stack is accompanied with a Dit reduction, but at the expense of a CET increase. Again, prepulsing with TMA lowers the Dit level as seen with the Al2O3 process down to a midgap Dit of ~8E11 /cm2eV (see Figure 2). However, in the case of a C-free AlSiOx process, a Dit increase is accompanied when prepulsing with TMA. For this process, a S-terminated InGaAs surface lowers the Dit of the formed gate stack and a similar level of ~8E11 /cm2eV can be reached.Finally, the incorporation of RE-oxides as an interfacial passivation layer was studied for both Al2O3 (4nm) and HfO2 (4nm). Both Sc2O3 ((MeCp)3Sc/H2O) and Gd2O3 (i(PrCp)3Gd)/H2O) were studied and in each case, the insertion of 4 ALD cycles reduces the Dit. The lowest Dit level was observed for Gd2O3 (~2E12/cm2eV independent of the cap layer).The oxide trap behavior for several of these gate stacks was also studied. An H2S treatment improves the oxide trap behavior slightly (~2% reduction of oxide traps). Shifting from a TMA based AlSiOx process to a C-free AlSiOx process yields a reduction of a factor ~1.5. However, the range of oxide traps for all these stacks is higher than 5e11/cm2 at the target field, which is still 1 order of magnitude too high.We demonstrate that the final gate stack passivation is dependent on the interaction between the In0.53Ga0.47As surface termination and the ALD precursors. A long TMA prepulse seems to be beneficial for most of the gate stacks but the improvement cannot be generalized. We demonstrate that the pretreatments used for Dit optimization of the Al2O3 stack, can also be applied in combination with HfO2. This means that we can reach similar Dit levels with a HfO2 based stack using the right pretreatment with large reduction in CET. Despite this improvement on interface traps, the improvement on oxide traps is not substantial. A further reduction of interface traps, will not yield a proportional device improvement 1. However, a further reduction of oxide traps is a prerequisite in order to introduce the IIIV channel materials into the 7nm technology node.[1] G. Hellings et al, IEEE Transactions on Electron Devices, 58(4), (2011), 938-944.[2] D. Lin et al., IEDM, (2012), p645-648.[3] J.B. Clemens et al., J. Chem. Phys., 133, (2010), 154702.