Engineering S/D Diffusion for Sub-100-nm Channel SOI MOSFETs

Abstract

This paper discusses the importance of controlling the lateral diffusion of impurities around the source and drain (S/D) junctions in sub-100-nm channel single-gate silicon-on-insulator (SOI) MOSFETs. Since any reduction in lateral diffusion length must consider the tradeoff between drivability and short-channel effect with regard to the threshold voltage, optimization of lateral diffusion length is essential in the device design stage. We note that the net performance improvement offered by device-scaling is quite limited, even if lateral diffusion length is optimized in some way. It seems obvious that high-/spl kappa/ materials are needed in order to improve net device performance in the sub-100-nm technology regime. In addition, with regard to the impact of the thermal budget on lateral diffusion control, new doping materials such as Sb and In, will be required in the near future. In the case of nMOSFET, however, advanced structures, such as an elevated layer, and advanced annealing process are needed to provide enhanced control of S/D diffusion regions.