Engineering of An Assertion-based PSLSimple-Verilog Dynamic Verifier by Alternating Automata

Abstract

Alternating Finite Automata (AFA) has linear space complexity in representing Linear-Time Temporal Logics. However, It is difficult to manipulate AFA in the run-time. In this paper, we focus on implementation methods to make alternating automata from static representation to run-time verification engines. 1) We have Directed Acyclic Graphs (DAG) represent all possible runs of a Local-variable-enhanced AFA (LAFA). The acceptance of universal choices is conditioned on successful synchronization of universal branches. 2) We encode states and local variables by symbolic approaches, and adopt historic trees in representing all possible parallel runs. The encoding enables multiple assignments to states and local variables in a configuration. By those methods, we are able to maintain the linear complexity of verification in both space and time.