Abstract
Solution processing and low-temperature annealing (T < 300°C) of the precursor compounds promise low-cost manufacturing for future applications of flexible oxide electronics. However, thermal budget reduction comes at the expense of increased charge trapping residuals in the dielectric layers, which result in hysteretic switching of transistors. This work reports on a novel bilayer dielectric scheme combining aluminum oxide (AlOx) as a positive charge trapping insulator and yttrium aluminum oxide (YAlOx) as a negative charge trapping dielectric to obtain hysteresis free switching in the solution-processed metal-oxide thin-film transistors. Devices were processed at a thermal budget of 250°C, without an encapsulation layer. The presence of H+ and OH− in the AlOx were found responsible for the hysteresis in the switching, which was suppressed successfully with the thickness optimization of the YAlOx in the dielectric stack. Fabricated devices yield ON/OFF ratios of 106, sub-pA level gate leakage currents, a subthreshold swing of 150 mV/decade, and field-effect mobility of 1.5 cm2/V-sec.
Highlights
The driving element of flexible electronics is the thin-film transistor (TFT), finding applications in flat panel displays (Barquinha et al, 2012), digital and analog circuitries (Petti et al, 2016), and sensors (Smith et al, 2014; Knobelspies et al, 2018)
We explore an alternative approach to engineering the dielectric stack using various insulators, with counterbalancing charge-trapping properties, when combined in a TFT offering minimal hysteresis
Initial experiments were conducted with devices having only one type of dielectric, i.e., aluminum oxide (AlOx) or yttrium aluminum oxide (YAlOx)
Summary
The driving element of flexible electronics is the thin-film transistor (TFT), finding applications in flat panel displays (Barquinha et al, 2012), digital and analog circuitries (Petti et al, 2016), and sensors (Smith et al, 2014; Knobelspies et al, 2018). It was observed that at the quasi-static frequencies, in addition to the readily existing high electric double-layer (EDL) capacitance, a bias dependent capacitance was present due to faradaic charge transfer at the interfaces of the dielectric with semiconductor and metal layers, which increased the gate capacitance by almost two orders of magnitude (the socalled pseudo capacitance effect). This effect was held responsible for the increased ON current in the transistors. Detailed electrical and chemical analyses were performed to shed light on the origin of the charge trapping mechanism
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